Conventional methods are generally limited to work only for the case where metal layer of driving buffer output pin shapes is immediately adjacent to the metal layer on which routing is to occur. Routing problems are exacerbated by the use of hierarchical wiring where the lower metal layers are finer pitch and thinner, and the upper wiring levels are thicker with a coarser pitch. For various reasons, buffer pins are often on lower, thinner wiring levels, where each wire is more resistive and carries less current reliably. More robust wiring methods are thus required to reliably route from lower thinner layers to the upper thicker layers when hierarchical wiring is used. Other related problems include the need to use fewer, larger, buffers to avoid a large variability that occurs when large numbers of small buffers are used in contrast with larger buffers that drive more loads.
FIG. 1 shows a system block diagram of a prior art computer system 100 that includes a central processing unit 110, a system memory 120, an input/output (I/O) controller 130, a network interface 140, and multiple interface units such as keyboard 150, monitor 160 and mass storage 170. The central processing unit 110 communicates with system memory 120, I/O controller 130 and other interface units via bus 180. The computer system 100 is shown having additional or fewer subsystems such as multiple processing units, external speaker device or a disk storage.
FIG. 2 illustrates a method for routing one or multiple low performance clock nets as known in the prior art. Referring to FIG. 2, a clock net 200 is illustrated with a driving buffer 210 and receiving buffer(s) 220. The driving buffer 210 is shown having multiple physical output pin shapes 230 on some metal layer (e.g., M9) and a physical input pin shape 240 on some metal layer (e.g., M5). One of the output pin shapes 230 is connected through path segment(s) 250 to the clock net routing 260 on some pair of metal layers (e.g., M10, M11) which in turn connect to the input pin shape(s) 240 of the receiving buffer(s) 220 through path segments 270, creating connections from the pair of routing metal layers (e.g., M10, M11) to the metal layer of the input pin shape (e.g., M5). The aforementioned solution can result in reliability violations when applied to high performance clock nets because the current carrying capability of the metal wires that constitute path segment(s) 250 are limited. Furthermore, path segment(s) 250 can introduce a high effective resistance resulting in large wire delays that violate wire delay limits for high performance applications.
FIG. 3 illustrates a method of routing one or multiple high performance clock nets as known in the prior art. The same clock net 200 is shown in FIG. 2 with a major difference being the description of a robust pin structure 380 on one of the routing metal layers (e.g., M10) which is connected to the output pin shapes 230 on some other metal layer (e.g. M9) of the driving buffer 210 with multiple parallel path segments 350 that interconnect the two adjacent metal layers (e.g., M9 and M10) using extended wire segments on M9 and vias to M10. Such a method requires that all the physical pin shapes of the output pin 230 of the driving buffer 210 be wired to the robust pin structure 380 that causes local wiring congestion and an increase of the power consumption of the integrated circuit. Furthermore, existing methods only work for the case where the metal layer of the output pin shapes (M9) and the metal layer of the robust pin structure(s) (M10) are adjacent layers that can be connected to each other using only one level vias.
In view of the aforementioned reasons, it is desirable to route high performance clock nets and other critical high-load nets in a wiring optimal manner while satisfying the electrical and reliability constraints to achieve reliability, performance and power-efficiency goals applicable to the high-performance chip designs.